The present invention relates to computer systems. More particularly, it relates to a virtual cache arrangement for use in such a computer system.
In the art relating to computer systems, it has been found that a significant limiting factor in the performance of large computers is the access time of a central processor unit to the Main Memory. The access time to the main memory in such computer systems is due largely to arbitration and bus delays in the memory access path. On the other hand, high speed random access memories (RAMs) provide a memory with a much faster access time. It is not, however, economically feasible to make a fast, large main memory from high speed random access memories.
It has been found that the effective access time of the memory of a large computer system may be improved, while the main memory continues to be of the relatively slow access type, by the addition of a smaller random access memory that is located close to and used exclusively by the CPU. That small random access memory has a much faster access time than the Main Memory and is referred to in the art as a cache memory. In at least one exemplary embodiment of a computer employing a cache memory, the cache had a capacity of 1,024 words while the Main Memory had a capacity for 256,000 words or more. Experience has shown that the locus of reference of computer programs is relatively small. In the exemplary structure hereinbefore noted, this system easily achieves a 90% hit ratio. That is, over an extended period of time, over 90% of the data requested from memory was found in the cache.
The conventional structure of a cache includes a Content Addressable Memory and a Data Memory. The Content Addressable Memory is used to relate the address supplied by the processor with a location in the Data Memory containing the value of the word. When the CPU makes a memory request, the address is presented to the Content Addressable Memory. If the content of that address is present in the cache, a "hit" occurs and this data may be fetched from cache. If the Content Addressable Memory does not indicate that the requested address is present, a "miss" occurs and the data must be fetched from the Main Memory in the usual way. As the data is read from the Main Memory, it is also loaded into the cache with the high probability that the CPU will request the content of that location in the near future.
While such cache memories have been successfully operated in a straight-forward system featuring a single central processor unit and a single Main Memory, complications have arisen where a plurality of data processors all have access to the one Main Memory. Although each of the central processors would have its own associated cache memory, there will be portions of the Main Memory which are shared by all of the CPUs. Thus, if a particular address from the Main Memory is stored in the cache associated with at least one of the CPUs, and another CPU then updates that data in the Main Memory, the data stored in the cache will be inconsistent with the data stored in the Main Memory resulting in an error if that data is called for.
Similarly, in recent practice, CPUs have been developed capable of multiple programming arrangements whereby the CPU may be operated intermittently under the control of several unrelated programs. If, under these conditions, the cache is associated with the CPU, every time the CPU switches to a different program, the "hit" rate of access to the cache drops dramatically because the data in the cache associated with the new program is unrelated to the old program and, hence, is drawn from a different portion of the Main Memory from that associated with another program. Therefore, the content of the cache at program switch time is irrelevant to the second or subsequent program. The necessity for reloading the cache each time the CPU switches from one program to another significantly slows the operation.
Typically, in present systems, the addresses in the processor are translated from the program address, or virtual address, to a memory, or physical address. That address translation is effected by an address translator, or mapper. The translation values are different for each program being run. For example, address "O" will be converted by the mapper into three different physical addresses for three programs A, B and C.
To access the contents of a memory location in the current systems, the CPU presents the virtual address to the mapper; the mapper converts the virtual address to a physical address; the physical address is then applied to the associative memory of the cache and a check for a "hit" is performed as hereinbefore described. Because physical addresses are used by the cache, operation must proceed sequentially with the virtual-to-physical address translation proceeding the cache look-up.